We often find that some of the rules or truths we take for granted often have some errors. Electronics engineers have an example of this in circuit design. Here is an engineer's summary of eight myths.

Phenomenon 1: The PCB design requirements of this board are not high, so use a thinner line and automatically cloth
    Reviews: Automatic wiring must occupy a larger PCB area, while producing many times more than manual wiring holes, in a large batch of products, PCB manufacturers to reduce the price of factors considered in addition to business factors, is the line width and the number of holes, they affect the PCB yield and the amount of drill consumption, saving the cost of suppliers, also to find a reason for the price reduction.

Phenomenon 2: These bus signals are pulled with a resistor, feel more assured
    Comments: There are many reasons why the signal needs to be pulled up and down, but not all of them should be pulled. Pull up and down resistance pull a simple input signal, the current is dozens of microamps below, but pull a driven signal, its current will reach milliamps, now the system is often 32 bits of address data, there may be 244/245 isolated after the bus and other signals, are pulled up, a few watts of power consumption on these resistors.

Phenomenon 3: How to deal with these unused I/O ports of the CPU and FPGA? Let's leave it empty. We'll talk about it later
    Comments: If the I/O port is not used, if it is suspended, a little interference from the outside world may become the input signal of repeated oscillation, and the power consumption of MOS devices is basically determined by the number of gate circuit reversals. If you pull it up, each pin will also have a microampere-level current, so the best way is to set it as an output (of course, no other driving signals can be connected outside).

Phenomenon 4: This FPGA has so many doors left to use, you can play to your heart's content
    The power consumption of FGPA is proportional to the number of triggers used and its number of flips, so the power consumption of the same model of FPGA at different times in different circuits may differ by 100 times. Minimizing the number of flip-flops at high speed is the fundamental way to reduce FPGA power consumption.

Phenomenon 5: The power consumption of these small chips is very low, do not consider
    Reviews: For the internal chip power consumption is not too complex is difficult to determine, it is mainly determined by the current on the pin, an ABT16244, no load then the power consumption is probably less than 1 mA, but its indicator is that each foot can drive 60mA load (such as matching tens of ohm resistance), that is, the power consumption of the full load is up to 60*16=960mA. Of course, only the power supply current is so large, the heat is falling on the load.

Phenomenon 6: There are so many control signals in the memory, I only need to use OE and WE signals on this board, and the chip selection is grounded, so that the data comes out much faster when reading operation
    Comments: The power consumption of most memory when the chip selection is effective (regardless of OE and WE) will be more than 100 times greater than when the chip selection is not effective, so CS should be used to control the chip as much as possible, and the width of the chip selection pulse should be shortened as long as other requirements are met.

Phenomenon 7: Why are these signals overrushed? If it's a good match, it can be eliminated
    Comments: In addition to a few specific signals (such as 100BASE-T, CML), are overrushed, as long as it is not large, it does not necessarily need to match, even if the match is not the best match. Like TTL output impedance is less than 50 ohms, and some even 20 ohms, if you also use such a large matching resistance, then the current is very large, the power consumption is unacceptable, and the signal amplitude will be too small to use, and the general signal in the output high level and output low voltage output impedance is not the same, there is no way to do a full match. Therefore, the matching of TTL, LVDS, 422 and other signals as long as the overshoot is acceptable.

Phenomenon 8: Reducing power consumption is all about hardware personnel, and has nothing to do with software
    Reviews: Hardware is just a stage, but the play is software, almost every chip on the bus access, every signal flip is almost controlled by software. If the software can reduce the number of accesses to external memory (more use of register variables, more use of internal CACHE, etc.), timely response to interrupts (interrupts are often low-level and have pull-up resistors), and other board-specific measures will make a great contribution to reducing power consumption.