In this Power Supply Design Tip, we will examine a simple circuit that can convert a high AC input voltage into a low DC voltage that can be used in applications such as electronic energy meters. In this particular application, there is no need to isolate the output voltage from the input voltage. Here, the rectified AC input voltage can be up to 375 VDC, while the output voltage at hundreds of milliamps can be less than 5 volts. These high-volume applications are often driven by cost and therefore require a low part count/low cost circuit. Step-down regulators offer a low-cost solution, but are challenging to implement with high voltage inputs. In continuous mode, the duty cycle of this step-down regulator is the output voltage divided by the input voltage, which is 1.25% when converting from 400V to 5V. If we run the power supply at 100 kHz, we need a turn-on time of 125 nS, which is usually impractical due to the switching rate limit.

Electronic System Design
FIG. 1 Low voltage buck IC enables a simple and economical biasing power supply

    Figure 1 shows a circuit that solves the duty cycle problem. The constant on-controller (U1) drives a high voltage step-down power stage that contains a P-channel FET (Q4) driven by a level conversion circuit (Q2, Q3) to convert 400V to 5V. This controller (the TPS64203 is used in our example) is key to this design. It has a low static current of 35 uA, allowing the converter to start offline with minimal R2 and R3 resistor power consumption. The second key factor is its ability to provide a short-time (600 nS) on-gate drive pulse to raise the minimum switching frequency (in continuous on-mode) above 20 kHz. Q1 is used for level switching gate drive voltages to high-end drivers. The low voltage output from the IC is about 5 volts on R4, which gives a fixed current in Q1 and R5. Voltage is supplied to R5 through the emitter output to the P-channel FET gate. The current also charges the C4 to power the drive circuit. We choose P-channel FET to simplify the drive circuit. If an N-channel is to be used, a method that can drive the FET gate above the input voltage is required to thoroughly enhance the device.

Electronic System Design
FIG. 2 MOSFETs exhibit good (< 50nS) switching speeds

    Figure 2 shows two circuit waveforms that indicate that good switching speeds can be achieved with a simple bipolar driver. A gate drive lift time of less than 50 nS produces a drain-switch time of less than 30 nS. The speed can be increased by adjusting the drive current converted to the P-channel FET at the cost of higher power consumption. The efficiency of this circuit is about 70%. Considering that the power consumption level is only 4 watts, the conversion from 400V to 5V, and the circuit is simple and cheap, this efficiency is not low. Two disadvantages of this design are the lack of short circuit and overvoltage protection. However, this circuit may represent a cost-effective compromise in many applications.