The TxP16S2TM is a high-performance 16-bit MCU operating at up to 13MHz with 128K FLASH and a total of 3K SRAM for high-performance processing of audio algorithms. It is a new generation of computing cores in the Flash Speech family. It initially targeted the field of voice applications to demonstrate its expertise. The TxP16S2 provides a fast unit that allows computation instructions to be issued simultaneously to the access memory in one cycle. The TRSF1602B is equipped with TxP16S2 and integrated I/O ports, audio PWM, timer and low voltage reset... Let's wait.
    In addition, the TRSF1602B extends its ability to connect external devices, such as serial ROM/Flash. Internal storage capacity includes 128Kx16 program/data FLASH and 3Kx16 working SRAM.

* High-performance RISC TxP16S2 CPU
- Wide operating frequency and voltage 6Mhz~13Mhz@1.8Volt~5.5 V
- The operating frequency can be programmed by software
- Built-in 3072x16 SRAM
- Embedded PC stack level 16
* Rich DSP features
- Hardware ring buffer support
-MAC Computing power: 13 MIPS (Max)
- Multi-function support: In MAC computing, access two operands in memory at the same time in one cycle
- Extended dynamic range: a 40-bit accumulator that ensures no overflow in 512 consecutive + addition operations
* Embedded flash 128Kx16
- Typical 1000 erase/programming cycles
- Data retention period of more than 10 years
* Software-based audio processing technology
-Subband, ADPCM, melody
* Supports 18+2 (ICE PAD can be used as I/O) universal I/O ports.
* Mono 16-bit PWM
*6 IRQ includes two external interrupts
*SPI main interface
* Three timers: Timer 1, timer 2, RTC timer
* Support spread spectrum timing to reduce EMI.
* Watchdog Timer (WDT)
* Low Voltage reset (LVR)
*PB0, PB1, PB2, and PB3 support two edge modes: rising edge trigger and falling edge trigger for wake-up function.
*IR
* Low voltage detector

*MCU applications
* Electronic Dictionary
* Handheld games
* E-Learning Assistance (ELA)
* Electronic storybook

    16-bit x 16-bit MAC is available for digital signal processing. The core of the MAC operation is the multiplication MX&MY using 2's complement operand and the sum of the previous 40-bit MF, and then rounding the stored result into the 40-bit MR To register the basic MAC architecture as shown in Figure 5.5.

Attention:
1. The VCC decoupling cap 10uF should be close to the IC within 0.5cm.
2.VCC decoupling cap 0.1uF should be close to IC 0.5cm.